Porsche’s electric race car; Autodesk, Ansys integration; FPGA-prototyping; Huawei thaw?
Porsche’s electric race car, the 99X Electric, used ANSYS Technology’s system-level simulation solutions to create an advanced electric powertrain. The powertrain is also being adapted for use in Porsche’s consumer electric cars. “ANSYS system-level simulations are instrumental for optimizing the Porsche E-Performance Powertrain’s motor, gearbox, power electronics and control software, allowing the Porsche 99X Electric to sustain unprecedented speeds over long distances while conserving as much energy as possible,” said Fritz Enzinger, vice president, Porsche Motorsport.
Synopsys completed its acquisition of La Jolla, Calif.-based DINI Group, which makes FPGA-based boards and IP for prototyping, low-latency networking, and high performance computing (HPC). Synopsys said in a press release that the FPGA-based boards will increase Synopsys’s portfolio of physical prototyping options for SoC designers working on automotive, 5G, networking, artificial intelligence (AI) and HPC.
Ansys and Autodesk have announced that their software now has “seamless interoperability across products” to cut down on extra steps for designers and engineers. Autodesk Fusion 360 results will now be available in ANSYS Mechanical simulation tools.
The U.S. state of Michigan announced it will add Mobileye 8 Connect aftermarket systems for collision avoidance to existing state and city fleets in a trial, pilot program.
Strategy Analytics says in a new report that the use of in-vehicle wired and wireless connectivity will expand this year with wireless implementations of Android Auto and Apple CarPlay, Wi-Fi, and adoption of USB-C, and the emergence of USB4. The analyst firms report also concludes that interest in ultrawideband (UWB) among suppliers and OEMs will increase for location tracking, including anti-theft.
Internet of Things
The low-power IP from Faraday Technology is now approved on UMC’s 22nm ultra-low-power (ULP) and ultra-low-leakage (ULL) processes. Faraday’s silicon-proven 22ULP/ULL fundamental IP has power reduction features. The IP and process combination is targeted at designers of low power SoCs for IoT, AI, comms and multimedia applications.
Ansys and Rockwell Automation are teaming up to help customers make digital twins for industrial environments. Rockwell is using Ansys Twin Builder.
UltraSoC joined the not-for-profit OpenHW Group devoted to furthering high-quality open-source hardware, tools and IP that is based on industry best practices. OpenHW Group and its 25 members contribute know-how to create the CORE V open-source cores based on RISC-V ISA. CORE V can be used as a short cut to design innovation in open-source hardware and manufacturability of SoCs.
Arm has been working on projects to get Kubernetes, Google’s former open-source software based on containers for automating application deployments, now managed by Cloud Native Computing Foundation (CNCF), onto device types, including edge devices. Kubernetes is heavy application, but Arm is helping others slim it down. Arm participates on the CNCF CI Working Group, whose goal is to provide full continuous integration and delivery (CI/CD) for CNCF projects. “Arm leads efforts on projects to bring Kubernetes to the edge, with initiatives including Project Cassini and partnerships focused on cloud native at the edge,” said a CNCF press release. Arm has also been working with Rancher Labs, which produces lightweight versions of Kubernetes called K3s that can be used on smaller devices. Arm is now a platinum member of CNCF, along with companies Amazon, Google, Apple, Intel, among others.
Accellera announced it has opened a Universal Verification Methodology–analog/mixed-signal (UVM-AMS) Working Group to standardize UVM-AMS extensions. Accellera manages EDA and IP industry standards.
Artificial Intelligence (AI)
Graphcore verified its large Colossus GC2 Intelligence Processing Unit (IPU) using Questa RTL simulation flow and Questa Verification IP (QVIP) for PCI Express. Questa software is used for simulation and verification of IP technologies. Mentor, a Siemens Business, makes Questa.
Aldec demonstrated its multi-FPGA partitioning software for multi-FPGA-based algorithm accelerators at Supercomputing19 on November 18-21, 2019 in Denver, Colorado. The automatic FPGA partitioning is a feature of Aldec’s HES-DVM software. The company also showed off DNN-based traffic detection using Xilinx Zynq US+ FPGA and Vibe Motion Detection.
The U.S. Commerce Department has approved some companies for licenses to sell technology to China’s Huawei. The Washington Post reports that the department approved roughly one-quarter of the nearly 300 license applications. The Department is issuing narrow licenses and “will continue to rigorously monitor sensitive technology exports to ensure that our innovations are not harnessed by those who would threaten our national security,” said Secretary of Commerce Wilbur Ross in a statement. Fifteen U.S. senators, however, are pushing back and asking Commerce Department to not issue narrow licenses.